1. Field of the Invention
The present invention relates to a fabrication process for a memory device. More particularly, the present invention relates to a fabrication process for a lower electrode of a memory capacitor.
2. Description of the Related Art
A capacitor is an important component of a dynamic random access memory (DRAM). In order to avoid mistakes in information stored in the DRAM, and to increase the operation efficiency of the DRAM, a three-dimensional capacitor having a large area, such as the common cylinder capacitor, is usually fabricated.
The conventional fabrication process for a lower electrode of a cylinder capacitor is as follows. First, a first insulating layer is formed on the substrate. Then, a node contact that has electrical connection with the substrate is formed in the first insulating layer. Afterwards, a second insulating layer is formed on the first insulating layer. An opening which exposes the node contact is provided in the second insulating layer. Then, a conductive layer, which functions as the lower electrode of the cylinder capacitor, is formed on the inner wall and the bottom of the opening. In the conventional fabrication process for a lower electrode of a cylinder capacitor, the template that forms the node contact and the lower electrode of a cylinder capacitor and the opening of the second insulating layer each require a photomask process. Thus two photomask processes are necessary. As a result, the conventional process not only wastes time, but also easily causes alignment problems.